Memory effects Induced by Space Charge Polarization in a SmNio 3 Film CNF

This report presents the first characterization of a correlated oxide SmNiO3 (SNO) used in electronic device structures. In a MOS capacitor with a gate insulator of a SNO film sandwiched between two SiO2 layers, memory effects are observed. The response time of polarization is over a microsecond. This implies that space charge polarization is dominant. Due to the instability of Ni3+ valence state, oxygen vacancies appear to lead to a polarization effect. In a MOSFET, counterclockwise hysteresis is observed, which is consistent with polarization switching effect. The stored information decays gradually with the retention time of around ten seconds. Summary of Research: Rare-earth nickelates RNiO3 (R stands for rare-earth elements such as Pr, Nd, and Sm) exhibit metal-insulator phase transition (MIT) as a function of temperature [1]. The MIT temperature increases with the size of the element [2]. At high temperature, the RNiO3 compounds are metallic with orthorhombic symmetry. As temperature decreases, charge disproportionation occurs between Ni sites, reducing the symmetry to monoclinic and resulting in a transition to an insulating state [3]. SNO is of particular interest because it is the first nickelate with MIT temperature above room temperature. Owing to instability of 3+ oxidation state of Ni, oxygen vacancies are present in a SNO film [2]. They lead to space charge creation and influence the conduction properties of SNO thin films. Space charge can affect the dielectric property of a SNO film. In this work, the dielectric properties of SNO are examined and the possibility of a memory application is also investigated. The MOSFET structure in the experiment is similar to that of a Flash memory and composed of a transistor with a SNO film employed as an intermediate gate insulator. The SNO film is sandwiched between thermal SiO2 and ALD SiO2 layers on a p-type silicon substrate. The MOS capacitor is the same gate structure as the MOSFET without Source and Drain (S/D) contacts except that it has an n+ silicon substrate. Figure 2: Frequency dependence of; (a) the gate capacitance, and (b) the hysteresis window of a MOS capacitor. Figure 1: Voltage hysteresis and temperature dependence of the gate capacitance of a MOS capacitor.